High precision analog devices need resistors with tight resistance control, a minimum possible absolute temperature coefficient of resistance (TCR) (i.e., the TCR should be as close to zero as possible) and excellent matching properties. These requirements can be fulfilled with metallic thin films made from low TCR alloys like NiCr, NiCrAI or SiCr. However, when integrating these kinds of resistors into existing process flows, special care has to be taken with respect to substrate planarity, accuracy of pattern definition and compatibility with standard interconnect processing, in particular etch selectivities and critical dimension (CD) losses. Often the desired performance can only be achieved by severe modifications to the manufacturing process, addition of multiple mask levels and/or narrower process windows. For example, in certain processes, integration of a SiCr thin film resistor results in three additional mask levels to the backend of the line because the resistor film is so thin that a direct connection with conventional interconnect vias is not possible. Instead, a local thin film VIA level and a resistor head level must be used.
FIG. 1 shows a semiconductor device 100 manufactured using such a conventional three mask level integration for a SiCr thin film resistor 104. A method for forming the device 100 is described in detail in U.S. Pat. No. 6,872,655.
An ultra thin SiCr layer 104 is deposited on a first intermetal dielectric 102 after a first chemical mechanical (CMP) planarization. The intermetal dielectric 102, as well as a metal layer 103, if required, is formed on a pre-metal dielectric (PMD) 101 and/or a first metal interconnect level. A thin film of insulating material 105 (for example tetra-ethyl-ortho-silicate (TEOS)) of the order of 1000 Å covers the SiCr resistor film 104 and an inter-level dielectric layer 107 is formed over the structure. Resistor heads 110 are formed on the thin film resistor 104. After formation of the resistor heads 110, the top portion of the first intermetal dielectric 102 is finalized. Finally the resistor head is connected to the second metal interconnect level 108 using conventional interconnect VIA1 processing. The resistor heads 110 act as an etch-stop layer for the vias 106 and have to be thick enough to sustain the higher overetch in the shallow openings for the vias 106. However, in order to form the structure shown in FIG. 1, three masking steps are required; a first to define the thin-film resistor layer 104, a second for creating the thin film via opening 106 and a third to form the resistor heads 110.
Solutions using fewer masks have already been proposed for thin film resistors. U.S. Pat. No. 6,737,326 discloses depositing a contacting metal directly on top of the resistor material, patterning metal lines together with the resistor body and then etching the contacting metal from the resistor body. However, the proposed method is only applicable to relatively thick resistor layers, as a thin SiCr thin film resistor layer cannot withstand the normal metal dry etch and the metal wet etch used for the contacting metal.